1. Field of the Invention
The present invention relates generally to semiconductor fabrication and, more particularly, to plasma etching chambers with controlled plasma volume using a plurality of confinement structures.
2. Description of the Related Art
In semiconductor fabrication, plasma etching is commonly used to etch conductive and dielectric materials. Plasma etch chambers are typically used which are capable of etching selected layers deposited over a substrate as defined by a photoresist mask. In general, the processing chambers are configured to receive processing gases, and radio frequency (RF) power is applied to one or more electrodes in the processing chamber. The pressure within the chamber is controlled in accordance with a particular desired process. Upon applying the desired RF power to the electrode(s), the process gases in the chamber are activated such that a plasma is created. The plasma is configured to perform the desired etching of the selected layers of a semiconductor wafer.
In order to perform the desired etching of the selected layers of a semiconductor wafer, the plasma is typically configured by manipulating variations in such parameters as pressure, electron density, flow rate, and the like. In order to achieve the desired plasma parameter variations within a single processing environment, examples of modifiable parameters include the chemistry of the gases, the pressure within the chamber, and the amount of RF power applied to the RF electrode(s) within the chamber. The prior art, however, does not provide for the variation of the volume of plasma within a single chamber. Without the ability to vary the volume of plasma in a single processing chamber, it is generally necessary to utilize a plurality of differently-configured processing chambers in order to achieve optimum plasma characteristics for particular etching applications. The plurality of processing chambers need to be compatible within a processing system of etch chambers, or capable of being positioned and operated in close proximity to other processing chambers to ensure economical and efficient wafer transfer between process chambers for the various stages of etch processing.
Dual damascene fabrication includes a common multi-step etching process which illustrates a range of processing environments required for optimum feature fabrication. FIG. 1A is a flow chart diagram 100 illustrating the method operations for the etching processes of a typical via-first dual damascene fabrication process. The flow chart diagram 100 begins after the substrate has been deposited with the various layers that will define fabricated features, and the first photolithography process has been performed to define the first etching operation. The first etch process is performed in operation 102 in which a via structure is etched. In a typical via etching operation, at least two dielectric layers are etched to form the via structure. FIG. 1B shows an exemplary substrate 120, over which has been deposited a barrier layer 126a, first dielectric layer 122, an optional etch stop layer 126b, and a second dielectric layer 124. A photoresist layer 128a has been patterned to enable the etching of a via 130 through the second dielectric layer 124, the etch stop layer 126b, and the first dielectric layer 122. In one example, the material properties of the first dielectric layer 122 and the second dielectric layer 124 are different and require that two separate etching operations using two distinct etch chemistries be performed to fabricate the via 130 structure. Returning to FIG. 1A, the first etch process 102 includes one or more etching operations required to completely define the via structure 130.
The method continues with operation 104 in which the remaining photoresist layer 128a (FIG. 1B) is removed. As is known, photolithography is used to define features in semiconductor manufacturing. In the instant example, the locations of the vias were first defined and then the via structures were etched. The remaining photoresist is removed in operation 104 so that the next feature can be defined and etched.
The method continues with operation 106 in which the next feature in the fabrication operation is patterned. By way of example, a next layer of photoresist is coated and then imaged to define the next feature, the trench structures. Using photolithography, the trenches are next defined in accordance with known feature fabrication processes.
The method advances to operation 108 in which the second etch process is performed. The second etch process in the instant example is the etching of the trench structures. FIG. 1C shows the exemplary structure of FIG. 1B in which a via 130 was etched as described in operation 102 above. The photoresist 128b has been removed to define the trench structure 132 which is etched through the second dielectric layer 124 and to the etch stop layer 126b. 
Returning once again to FIG. 1A, the method advances to operation 110 in which the remaining photoresist 128b (Figure 1C) is removed. Once the second etch process is completed and the trench structures are fabricated, the remaining photoresist used to define the trench structures is removed.
The method continues with operation 112 in which the silicon nitride (SiN) layers are etched, and the method is done. FIG. 1D shows the completed features defined using etching processes in the example fabrication of a dual damascene structure. The barrier layer 126a that was within the via feature 130 is etched to expose the substrate 120. The etch stop 126b that was in the trench feature 132 between the first dielectric layer 122 and the second dielectric layer 124 is likewise etched. Both the etch stop 126b, an optional layer depending on the particular structure and process, and the barrier 126a are typically layers of SiN, the removal of which are the final etching steps in the instant dual damascene fabrication example. As is known, the etching processes are typically followed by deposition of barriers and/or metallization to fabricate the trenches and vias of the dual damascene structure.
As illustrated in the flow chart diagram 100 of FIG. 1A, at least three separate etching, and two photoresist removal, operations are performed in the etching processes of a typical dual damascene fabrication operation. As will be described in greater detail below, the first etch process is best suited for a large volume plasma etch environment. Typically, in a large volume environment, high ion energy, also known as high bias voltage, is achieved at the surface of the substrate. In a large volume environment, high plasma flow rate is achieved at a low pressure. Because the first etch process includes etching through two dielectric layers in addition to an optional SiN etch stop layer, the higher bias at a higher flow rate are the desired plasma characteristics. A high plasma volume containment environment provides the optimal conditions for the most effective and efficient plasma.
The removal of photoresist is most optimally performed in a small volume oxygen plasma environment. In a small volume environment, the plasma is maintained very close to the surface of the wafer. The plasma achieved is generally very high density, and yields a very high photoresist removal rate. Additionally, in a small volume environment, ion energy to the wafer is low so that sputtering of the dielectric material can be minimized. A small plasma volume containment environment is generally desired for photoresist removal.
The second etch process can be either a large plasma volume environment or a small plasma volume environment, and needs to be optimized in accordance with the materials utilized. By way of example, the etch stop layer 126b (FIGS. 1B, 1C, and 1D) is an optional layer. Further, the first dielectric layer 122 and the second dielectric layer 124 can be of various similar or disparate dielectric materials, and their particular material properties dictate the etch chemistries needed to etch the second dielectric layer 124 down to the optional etch stop layer 126b or the first dielectric layer 122. If an etch stop layer 126b is used, a small plasma volume containment environment is commonly used to achieve a high etch rate. Generally, either a large volume or a small volume containment is selected depending on materials and configuration which will provide the best etching uniformity across the wafer.
Finally, the SiN etch is typically optimal in a small plasma volume containment environment to achieve high plasma density which yields high etch rate and low ion energy toward the wafer. Low ion energy toward the wafer will minimize the sputtering of dielectric material which is underneath the SiN layer.
FIG. 2A is a block diagram of a typical small plasma volume containment environment in an etch chamber 140. A wafer 146 is positioned on a lower electrode 144, and an upper electrode is located over the wafer 146 and defining a region of plasma containment 145 between the upper electrode 142 and the wafer 146. In one embodiment of a small plasma volume containment in an etch chamber 140, a plurality of containment rings 148 are disposed between an outer edge of the wafer 146 and an inner wall of the chamber 140, and defining a lateral boundary of the plasma containment region 145. The containment rings 148 are rings within the cylindrical structure of the etch chamber 140 of a desired width and spacing to define a plasma containment area 145 within, and to allow for the spent gasses of the plasma to flow outward and exhaust from the etch chamber 140. The containment rings 148 serve as a slotted confinement shield with each ring comprised of a dielectric such a silica or quartz. For a detailed description of a small plasma volume confinement chamber, reference is made to U.S. Pat. No. 5,534,751, issued on Jul. 9, 1996 to the same assignee as the present application, and which is herein incorporated by reference.
FIG. 2B is a block diagram of a typical large plasma volume containment environment in an etch chamber 140. A wafer 146 is positioned on a lower electrode 144, and an upper electrode is positioned over the wafer 146 and defining a region of plasma containment 145 between the upper electrode 142 and the wafer 146. In the large plasma volume containment environment, a plasma confinement structure 150 is positioned at a distance far enough away from the wafer 146 to provide for a large volume for plasma flow. The plasma confinement structure 150 can be physical with apertures in structures constructed of materials such as quartz or silica to allow for the neutral species of the plasma to flow outward and exhaust from the etch chamber 140 ensuring the dissipation of ion energy prior to exhaust. The plasma confinement structure 150 can also be magnetic with the magnetic energy expelling the ions and the electrons, or charged species, from passing through the confinement structure of the etch chamber 140. For a detailed description of an etch chamber configured for large plasma volume confinement, reference is made to U.S. Pat. No. 6,170,429, issued on Jan. 9, 2001 to the same assignee as the present application, and which is herein incorporated by reference.
As described above, the plasma etching operations of an exemplary multi-step semiconductor fabrication process can require a plurality of plasma volume environments to optimize the required etching process. What is needed is a single plasma etch chamber that can be configured for either small plasma volume containment or large plasma volume containment. The single chamber should be capable of being configured to a plasma etch system incorporating a plurality of such configurable chambers to increase efficiency and throughput while decreasing downtime and cost of operation.
Broadly speaking, the present invention fills these needs by providing a plasma processing chamber that is configurable for a plurality of plasma volume applications.
In accordance with one aspect of the invention, a plasma processing chamber is provided. The plasma processing chamber includes a bottom electrode configured to support a substrate for processing, and a top electrode located over the bottom electrode. The plasma processing chamber also includes a plasma confinement assembly which is designed to transition between a closed orientation and an open orientation. In the closed orientation, the plasma confinement assembly defines a first volume for plasma during processing, and in the open orientation, the plasma confinement assembly defines a second volume for plasma during processing which is larger than the first volume.
In accordance with another aspect of the invention, a plasma etch process chamber having configurable plasma volume is provided. The plasma etch process chamber includes configurable plasma confinement rings that defined a plurality of separate parallel passages that allow gas flow through the rings. The configurable plasma confinement rings are disposed around a pair of parallel electrodes which defines a first plasma confinement region where a plasma is generated and confined by the parallel passages which neutralize ion particles in the plasma when they pass through the parallel passages. The configurable plasma confinement rings are configurable to be positioned in an extended position defining the first plasma confinement region, and in a retracted position which defines a second plasma confinement region. The plasma etch process chamber further includes an upper chamber liner configured to line an upper region of the plasma etch process chamber and having an outer plasma confinement structure with a plurality of apertures.
In accordance with yet another aspect, a semiconductor wafer processing chamber having a configurable plasma volume is provided. The chamber includes an upper electrode and a lower electrode which is parallel to the upper electrode and is configured to receive a semiconductor wafer for processing. The chamber further includes a first plasma confinement region. The first plasma confinement region has the upper electrode as an upper boundary and the lower electrode as a lower boundary. A second plasma confinement region is defined which has the upper electrode as an upper boundary, the lower electrode as a lower boundary, and an upper chamber liner as a lateral boundary The upper chamber liner lines an upper region of the semiconductor wafer processing chamber and is configured with an outer plasma confinement structure. The chamber further includes a plasma confinement assembly which has at least one plasma confinement ring, a plurality of spacers, and a plurality of shafts. The plasma confinement assembly is positioned within the semiconductor wafer process chamber, is disposed around the first plasma confinement region, and defines a plurality of parallel circumferential passages. The plasma confinement assembly is configured to be positioned in an extended position to defined the first plasma confinement region, and in a retracted position to define the second plasma confinement region.
The advantages of the present invention are numerous. One notable benefit and advantage of the invention is that a single chamber can be configured for a plurality of plasma etch processes. Typically, in order to achieve the benefits offered in the single chamber of the present invention, it has been necessary to either combine a plurality of chambers often from different manufactures. With the size and expense of system tools and the cost of obtaining and operating fab space, duplication of tools is not an economical or efficient option. The present invention provides for maximizing efficiency and economy by providing a single chamber that can be configured for a plurality of precision plasma etch processes.
Another significant advantage is the ability to optimize the plasma etch processes in a single system or chamber. In multi-step plasma etch processes, intermediate etching operations often require specific configuration to achieve optimum etch for a particular process. Typically, in the prior art, a choice is elected to either achieve the best possible etch result for the plurality of etch processes with a single tool in a set configuration, or to combine separate machines and systems to achieve the desired configurations for specific processes from different chambers. Single tool configurations typically result in less than optimal processing, and the combination of separate machines and systems typically results in increased expense, increased transfer and handling time, and increased potential for contamination. Operating and maintaining entire systems, often from different manufacturers, for individual process steps significantly increases the cost of operation in such areas as maintenance, training, and fab floor space and configuration, in addition to the individual equipment costs.
Another advantage of the present invention is the increased throughput with decreased cost of operation. The present invention provides for both clean operation and for deposition operation. By performing both operations in a single chamber, the useful life of consumables such as chamber liners is increased, down time for wet cleans and other clean and/or maintenance operations is reduced when spread across a range of etch processes, and throughput is therefore increased with a more efficient utilization of production equipment.